1. Field of the Invention
The invention relates to a method for manufacturing semiconductor devices and, more particularly, to the method for manufacturing semiconductor devices by packaging a semiconductor chip onto a wiring board by use of a flip-chip approach.
2. Description of the Related Art
To manufacture a semiconductor device represented by an LSI (Large Scale Integration) such as a microprocessor, a memory, or a like, it is necessary to package onto a wiring board a semiconductor chip in which desired circuits are incorporated. To thus package the semiconductor chip, there have been known the following two approaches conventionally.
One approach is a face-up approach, whereby the semiconductor chip is packaged onto a wiring board with its right face facing upward on which pads are formed electrodes. According to this face-up approach, pad electrodes of the semiconductor chip are bonded with a wire to their corresponding wiring portions on the wiring board, thus being connected to an outside of the semiconductor chip. An other approach is a face-down approach, whereby the semiconductor chip is packaged onto the wiring board with its right face facing downward on which its pad electrodes are formed, an outgrowth of which approach is known as a flip-chip approach using ball-like solder electrodes (solder bumps) for connection. According to this approach, the ball-like solder electrode is formed at each pad of the semiconductor chip and connected to its corresponding wiring portion on the wiring board, thus being connected to the outside of the semiconductor chip.
As can be appreciated from comparison between the above-mentioned two approaches of packaging, the flip-chip approach eliminates a process of wire bonding and, moreover, is advantageously capable of connecting a number of ball-like solder electrodes to the wiring board simultaneously, thus tending to be employed preferably in manufacturing of LSIs having an ever increasing number of pins with increasing integration densities and functions required.
The following will describe the above-mentioned method of manufacturing semiconductor devices with reference to FIGS. 7A, 7B, 7C, 8A, 8B, 9A and 9B.
First, as shown in FIG. 7A, a semiconductor chip 51 is prepared in which a number of ball-like solder electrodes 52 made of high-melting-point solder are connected onto a right face of the semiconductor chip 51. Next, as shown in FIG. 7B, flux 53 is coated, to improve solderability, to the right face of the semiconductor chip 51 on which the ball-like solder electrodes 52 are formed. This flux 53 coating is performed by immersing that right face of the semiconductor chip 51 in for example a flux tub filled with flux 53. Next, as shown in FIG. 7C, a wiring board 55 is prepared which includes a multi-layer wiring board and a number of eutectic solder bumps 54 connected thereto, so that on this wiring board 55 is mounted the semiconductor chip 51 in such a manner that its ball-like solder electrodes 52 may be aligned with corresponding eutectic solder bumps 54 and then, as shown in FIG. 8A, the eutectic solder bumps 54 are melted, thus packaging the semiconductor chip 51 to the wiring board 55 (primary packaging). This semiconductor-chip packaging process is performed by moving the wiring board 55 mounted with the semiconductor chip 51 as mentioned above, into a solder reflow furnace.
Next, to remove residual flux remaining on the right face of the semiconductor chip 51 or that of the wiring board 55, it is washed to remove the flux. This flux removal by washing has been conventionally performed specifically by immersing the wiring board 55 as mounted with the semiconductor chip 51 thereon into a washing tub and by applying supersonic waves to a washing solution. Next, as shown in FIG. 8B, a resin is injected to an under-fill portion 56 sandwiched between the semiconductor chip 51 and the wiring board 55, which is followed by a cure process to harden the resin, thus forming an under-fill resin 57. By the above steps, a main portion of the semiconductor device is manufactured.
Next, as shown in FIG. 9A, a radiation plate 58 is attached to a back face of the semiconductor chip 51 and then, as shown in FIG. 9B, ball-like solder electrodes 59 for use in secondary packaging are connected onto a back face of the wiring board 55, thus completing the semiconductor device.
The conventional method for manufacturing semiconductor devices, however, has a problem in that a process of flux removal by washing performed after a semiconductor chip 51 is mounted onto a wiring board 55 is not capable of completely removing the flux, thus leaving residual flux.
That is, as mentioned above, even when the wiring board 55 mounted with the semiconductor chip 51 thereon is immersed into the washing tub and washed therein, the flux cannot completely be removed, to leave part of its organic film on the right face of the semiconductor chip 51 or that of the wiring board 55, thus generating flux residue. This may be because a distance between the ball-like solder electrodes 52 of the semiconductor chip 51 is extremely small and, at a same time, distance between the semiconductor chip 51 and the wiring board 55 is also small, thus suppressing full exertion of stirring effects by the supersonic wave in the washing solution. Such flux residue may be formed increasingly, taking into account that the distance between the ball-like solder electrodes 52 will be smaller with an ever increasing number of pins of a future LSI.
Although such a conventional method has been worked out that employs, instead of the supersonic-wave approach, a shower approach for spraying a washing solution to the under-fill portion 56 to wash off the flux, this shower approach cannot avoid the above-mentioned disadvantage either because it also finds it difficult to permit the washing solution to go sufficiently around an extremely small area between the ball-like solder electrodes 52 as well as narrow under-fill portion 56 sandwiched between the semiconductor chip 51 and the wiring board 55.
As mentioned above, if the flux residue is generated, the following process of injecting a resin to the under-fill portion 56 suffers from a poor flowability of the resin. That is, the flowability of the resin degrades because flow of the resin is inhibited by action of the organic film of the flux left on the right face of the semiconductor chip 51 or that of the wiring board 55. Therefore, the resin cannot completely be injected to the under-fill portion 56, thus always giving rise to a void in the under-fill resin 57 when it is being injected. The void thus generated in the under-fill resin 57 may contribute to a poor continuity between the semiconductor chip 51 and the ball-like solder electrodes 52 when a completed semiconductor device is packaged onto a mother board of an electronic apparatus (secondary packaging).
As shown in FIG. 10A, a void 60, if generated in the under-fill resin 57 when the resin is injected, may expand over melted ball-like solder electrodes 52, as shown in FIG. 10B, because of heat treatment conducted when the semiconductor device is secondary-packaged to the mother board, to deform mutually adjacent ball-like solder electrodes 52, thus resulting in short-circuiting therebetween.
Also, poor flowability, due to occurrence of the flux residue, of the resin during a process of injecting the resin to the under-fill portion 56 brings about longer time required for resin injection, thus affecting manufacturing costs.
In view of the above, it is an object of the invention to provide such a method for manufacturing a semiconductor device that improves flowability of a resin when it is injected to an under-fill portion, thus preventing a void from occurring in an under-fill resin during a resin injection process and also shortening a time required for that process.
According to an aspect of the present invention, there is provided a method for manufacturing semiconductor devices for packaging a semiconductor chip onto a wiring board by a flip-chip approach and then injecting a resin to an under-fill portion between the wiring board and the semiconductor chip, including the steps of:
preparing, as a flux-coating step, the semiconductor chip onto a right face of which are connected ball-like solder electrodes and then coating flux onto the right face of the semiconductor chip;
preparing, as a semiconductor-chip packaging step, the wiring board onto a right face of which are connected eutectic solder bumps and mounting the semiconductor chip onto the wiring board in such a way that the ball-like solder electrodes may be aligned with the eutectic solder bumps and then melting the eutectic solder bumps, to thereby package the semiconductor chip onto the wiring board;
forcedly spraying, as a flux wash-off step, a washing solution to the under-fill portion, to wash off the flux coated to the under-fill portion;
exposing, as a plasma processing step, to a plasma atmosphere the wiring board mounted with the semiconductor chip thereon, to subject the wiring board to plasma processing; and
injecting the resin to the under-fill portion as an under-fill resin-injection process.
In the foregoing, a preferable mode is one that wherein further including the step of, after the under-fill resin-injection process, a packaging ball-like solder electrode-connection step of connecting packaging ball-like solder electrodes onto a back face of the wiring board.
Also, a preferable mode is one that wherein further including step of a radiation-plate mounting process of mounting a radiation plate onto a back face of the semiconductor chip after the under-fill resin-injection process and before the packaging ball-like solder electrode-connection step.
Also, a preferable mode is one wherein the plasma processing step is specifically performed by performing plasma processing by use of oxygen, argon, or a gas mixture of oxygen and argon.
Also, a preferable mode is one wherein a melting point of the ball-like solder electrodes of the semiconductor chip is higher than a melting point of the eutectic solder bumps of the wiring board.
Also, a preferable mode is one wherein the ball-like solder electrodes of the semiconductor chip are made of solder having a high melting point.
Also, a preferable mode is one wherein the packaging ball-like solder electrodes of the wiring board are made of eutectic solder.
Also, a preferable mode is one wherein a region where the ball-like solder electrodes are not connected onto the right face of the semiconductor chip is covered with an insulator protection film.
Furthermore, a preferable mode is one wherein a region where the eutectic solder bumps are not formed on the right face of the wiring board is covered with an insulator protection film.
Still furthermore, a preferable mode is one wherein the wiring board makes up of a multi-layer wiring board.